The present invention relates to a gate driving circuit that corrects deviation of switching timing of self-extinction semiconductors that are connected in series.
FIG. 15 is a circuit structure diagram that shows prior art semiconductor equipment described in Japanese Patent Application Laid-open Publication No. 11-262243. What is shown are gate driving circuits for MOS gate input self-extinction semiconductors that are connected in series. Reference numbers 50-1, 50-2, and 50-3 denote self-extinction semiconductors that are connected in series. Each of the self-extinction semiconductors 50-1, 50-2, and 50-3 receives a normal switching signal through a gate resistor 51, switches 52 and 53, and DC power sources 54 and 55, based on a switch signal control signal 56.
When a plurality of self-extinction type semiconductors are connected in series, the following problem occurs. That is, when the characteristics of the self-extinction type semiconductors or their driving unit change with time, or when the switching pattern has changed to change the temperature of the device, resulting in the occurrence of a difference in the characteristics, the switching timing of the self-extinction type semiconductors varies. This generates a difference in the transient bearing of voltage. In this case, the deviation of the switching timing is corrected as follows.
When the switching timing has deviated at the time of turning off the series-connected self-extinction type semiconductors, this deviation is corrected with a gate resistor 57, a switch 58, a DC power source 59, a driving circuit 60, a current detector 61, and a logic processing circuit 62. In other words, the current detector 61 detects a difference in currents that flow through upper and lower snubber circuits 70 that are connected in series, and detects a deviation in the switching timing at the turn-off time. The timing deviation is corrected by controlling a mirror period based on this detection.
When the switching timing has deviated at the time of turning on the series-connected self-extinction type semiconductors, this deviation is corrected with the gate resistor 57, a switch 63, a DC power source 64, a resistor 65, a reference power source 66, a comparator 67, a driving circuit 68, and the logic processing circuit 62. In other words, a large current flows to a gate terminal during a mirror period, thereby increasing turn-on speed. The deviation in the switching timing is reduced based on this increased turn-on speed.
Based on the above structure, the prior art semiconductor equipment reduces a deviation at the turn-on timing by increasing the turn-on speed. Therefore, a current change rate becomes high, and at this time, a recovery surge voltage that occurs in a freewheeling diode of the other arm becomes large. The surge voltage becomes higher when the timing variation is made smaller. It is possible to increase the turn-on speed only to a level at which the surge voltage is within a rated reverse voltage of the freewheeling diode. Therefore, it has not been possible to reduce the timing deviation at the turn-on timing to a sufficiently small level.
Further, the timing deviation at the turn-off time, is corrected based on the difference in currents that flow through the upper and lower snubber circuits that are connected in series. Therefore, when three transistors of early turn-off timing continue, and a transistor of late turn-off timing is connected to the above, for example, only the turn-off timing of a top transistor among the transistors of early turn-off timing is corrected to be late. The turn-off timing of the remaining two transistors of early turn-off timing is not corrected. Therefore, it has not been possible to accurately correct the timing deviation.
It is an object of this invention to provide a semiconductor equipment that is equipped with a gate driving circuit that can properly adjust a deviation in the switching timing.
The semiconductor equipment according to one aspect of the present invention comprises a plurality of self-extinction type semiconductors connected in series, each of the self-extinction type semiconductors having a control terminal; and a control signal generator that generates a predetermined switching control signal for controlling the self-extinction type semiconductors. Corresponding to each of the self-extinction type semiconductors there are provided an overvoltage protector that protects the self-extinction type semiconductor when an overvoltage has occurred in the self-extinction type semiconductor; and a switching timing adjuster provided between the control terminal of the self-extinction type semiconductor and the control signal generator. The switching timing adjuster has an input decision circuit that decides that a signal output from the overvoltage protector is a signal that has been output based on an occurrence of an overvoltage in the self-extinction type semiconductor due to a deviation in the switching timing at a turn-on or turn-off time; a signal holding circuit that holds a signal corresponding to the overvoltage that is output from the input decision circuit; and a pulse formation circuit that forms a corrected switching control signal based on a signal held in the signal holding circuit and a switching control signal from the control signal generator.
The semiconductor equipment according to another aspect of the present invention comprises a plurality of self-extinction type semiconductors connected in series, each self-extinction type semiconductor being connected with an overvoltage protector. A switch is provided which electrically disconnects the self-extinction type semiconductor and the overvoltage protector before the self-extinction type semiconductor is turned on.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.